1. Field of the Invention
The present invention relates to the field of semiconductor devices and more particularly to a semiconductor device having a source/drain region comprising a semiconductor portion and a metal portion.
2. Discussion of Related Art
In order to increase the performance of modern integrated circuits, such as microprocessors, silicon on insulator (SOI) transistors have been proposed. Silicon on insulator (SOI) transistors have an advantage in that they can be operated in a fully depleted manner. Fully depleted transistors have an advantage of an ideal subthreshold gradient for optimized on-current/off-current ratios. An example of an proposed SOI transistor which can be operated in a fully depleted manner is a tri-gate transistor 100, such as illustrated in FIG. 1. Tri-gate transistor 100 includes a silicon body 104 formed on insulating substrate 102 having a buried oxide layer 103 formed on a monocrystalline silicon substrate 105. A gate dielectric layer 106 is formed on the top and sidewalls of silicon body 104 as shown in FIG. 1. A gate electrode 108 is formed on the gate dielectric layer and surrounds the body 104 on three sides essentially providing a transistor 100 having three gate electrodes (G1, G2, G3) one on each side of silicon body 104 and one on the top surface of the silicon body 104. A source region 110 and a drain region 112 are formed in the silicon body 104 on opposite sides of the gate electrode 108 as shown in FIG. 1. An advantage of the tri-gate transistor 100 is that it exhibits good short channel effects (SCE). One reason tri-gate transistor 100 has good short channel effects is that the nonplanarity of the device places the gate electrode 108 in such a way as to surround the active channel region. Unfortunately, as tri-gate devices become increasingly smaller, the external contact resistance (Rext) is increasingly becoming more significant portion of the overall device resistance. This is particularly problematic in three dimensional transistors (formed both by etching of Si wafer, or by chemical synthesis of nanowires), where the source region 110 and drain region 112 are formed in the narrow silicon body 104. Unfortunately, standard techniques for reducing contact resistance, such as by forming “raised” source/drain regions where additional epitaxial silicon is formed on the silicon body 104 is difficult to implement in nonplanar transistors. For example, it is difficult to grow “raised” epitaxial source/drain regions on the sides of the silicon body 104. For these reasons the devices suffer from high Rext and degraded performance.